What is IBM’s nanostack chip architecture?
IBM announced a new sub-1 nanometer nanostack chip architecture that stacks transistors vertically instead of horizontally, promising nearly double the transistor density of current 2nm chips. Cody leads skeptically: the announcement is a capability claim without shipping proof, and the fabrication challenges—wafer-to-wafer bonding precision, High NA EUV maturity, and unknown yield at volume—are enormous. Justy pushes back: the material-decoupling unlock (optimizing n-type and p-type transistors independently) is real, and for AI accelerators, the power efficiency gains directly address data-center bottlenecks. They land on a shared reading: IBM's architecture is mechanistically sound and the roadmap credible, but this is a research milestone, not a product—and the gap between lab demo and foundry-scale manufacturing is where most announcements die.
Transcript
Justy So IBM just announced this nanostack thing—vertical transistor stacking, basically—and the power claims are huge. You're going to hate this.
Cody I don't hate it yet. But okay, let me poke at it: they're claiming a capability, not a product. <cite index="2-2">Sub-1 nanometer chip technology at the 0.7 nm node</cite>, near-100-billion transistors, seventy percent power savings. That's the press release. What's actually shipping?
Justy Right—
Cody The announcement is a lab demo. <cite index="1-1">Wafer-to-wafer bonding requires tightly controlling how flat the wafers are and proper alignments of transistors relative to one another</cite>. That's 18-nanometer pitch alignment. That's not solved at scale. And then you layer on <cite index="1-5">High NA EUV lithography equipment that's slated to be available later this year</cite>—it's not even in the fab yet. This is faith-based: two separate bets that both have to work t
Justy Wait, but the material thing. That's the part I actually think wins here.
Cody Mm-hm.
Justy So the whole constraint of the last sixty years is you're building n-type and p-type transistors side by side. You're stuck compromising on materials—what's best for p-type isn't what's best for n-type. Now you can decouple them, stack them vertically, and optimize each material independently. That's not marketing. That's a real architectural unlock.
Cody Okay, that part is sound. I buy the architecture.
Justy Right. And for AI accelerators, the power story matters. Seventy percent less energy consumption than 2 nm—that's not noise.
Cody It's not noise if it ships. But here's where I get stuck: yield. Defect density at this scale, especially with vertical bonding and sub-18-nanometer wiring. They don't talk about it. The announcement is all capability ceiling, zero manufacturing floor.
Justy They've got a roadmap—five years to production—
Cody Which is fine. But IBM's been right about fab physics before. They're not making this up. The real question is whether High NA EUV actually matures on schedule and whether the bonding precision holds at volume. Those are two separate problems that have to both solve.
Justy Okay, fair. So the architecture is legit, the power gains are real, but you're asking: does it actually make it out of the lab?
Cody Exactly. And here's the thing—if it does, it changes the constraint for another decade. <cite index="2-1,7-4">Forty percent scaling in SRAM compared with state-of-the-art non-stacked cells</cite>. That's the largest SRAM density jump in years. For data-center chips, that's real.
Justy Yeah. And I think that's why the power story actually lands. Data-center power budgets are the constraint now, not transistor count. You're right that bonding and yield are enormous questions. But if IBM ships this, it's not just a scaling win—it's constraint relief on the actual bottleneck.
Cody Okay, so we've both decided the same thing: the architecture is sound, the roadmap is credible, and we have absolutely no idea if it works at scale.
Justy That's such an Exploring Next take.
Cody It really is. We've become the people who say 'the mechanism is real but the manufacturing is a nightmare' and call that a conclusion.
Justy That's your life now. You wanted to understand how things actually work.
Cody I regret nothing. But yeah, nanostack is the right move architecturally. <cite index="3-2">IBM and partners including Lam Research, Tokyo Electron, and SCREEN have been working together to develop new High NA EUV processes and tools that have already yielded working devices</cite>. The question is whether that scales from demonstration to foundry. Ask me in five years.
Justy Five years is fair. And honestly, the fact that they're already running High NA EUV in the lab and getting working devices is... I don't want to say impressive, but it's not nothing.
Cody It's not nothing. It's a real checkpoint. But checkpoints are easy. Volume is hard.
Justy True. But if this lands, AI chips get faster and cooler—literally and figuratively. That's the user story. Data centers stop melting.
Cody Right, and that matters. But I'm not betting my prediction on IBM's optimistic timeline.
Justy Of course you're not. You're doom-peddling until it ships.
Cody My job. But I genuinely think the nanostack unlock is real. The execution is the unknown.
Justy That's the most honest thing you've said about this. And I'm going to say the same thing back: the material decoupling is a real architectural win. Whether it makes it to your laptop in five years is a different bet. Fair?
Cody Fair. And that's where we land.